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nt96 650 bg - es 2012 - 09 - 17 - 1 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. nt96 650 - es hybrid dsc/dv processor version 0.3 confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 2 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. table of contents revision history ................................ ................................ ................................ ........................... 4 features ................................ ................................ ................................ ................................ .......... 5 general description ................................ ................................ ................................ ................. 11 block diagram ................................ ................................ ................................ ............................ 12 pin configuration ................................ ................................ ................................ ...................... 13 tfbga - 305 ................................ ................................ ................................ ................................ ........................ 13 pin descriptions ................................ ................................ ................................ ......................... 16 nt96 650b g 305 pins ................................ ................................ ................................ ................................ ......... 17 system interface ( 9 ) ................................ ................................ ................................ ................................ ....................... 17 rtc & power button cont roller ( 7 ) ................................ ................................ ................................ .............................. 17 dram interface ( 48 ) ................................ ................................ ................................ ................................ ..................... 17 sensor interface ( 33 ) ................................ ................................ ................................ ................................ ...................... 18 memory card interface ( 29 ) ................................ ................................ ................................ ................................ ........... 21 lcd interfa ce ( 23 ) ................................ ................................ ................................ ................................ ......................... 22 pwm ( 20 ) ................................ ................................ ................................ ................................ ................................ ...... 25 peripheral i/o ( 19 ) ................................ ................................ ................................ ................................ ......................... 26 adc interface ( 8 ) ................................ ................................ ................................ ................................ ........................... 27 audio codec(10) ................................ ................................ ................................ ................................ ............................ 27 tv interface (2) ................................ ................................ ................................ ................................ .............................. 28 mip i dsi (7) ................................ ................................ ................................ ................................ ................................ .. 28 hdmi (13) ................................ ................................ ................................ ................................ ................................ ..... 28 usb device interface (4) ................................ ................................ ................................ ................................ ................ 29 power ( 73 ) ................................ ................................ ................................ ................................ ................................ ...... 29 package outline ................................ ................................ ................................ ......................... 31 tfbga - 305 ................................ ................................ ................................ ................................ ........................ 31 electrical character istics ................................ ................................ ................................ . 32 a bsolute m aximum r atings ................................ ................................ ................................ .............................. 32 confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 3 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. esd performance ................................ ................................ ................................ ................................ ............. 32 l atch - up i mmunity ................................ ................................ ................................ ................................ ............. 33 r ecommended o p erating c onditions ................................ ................................ ................................ .............. 33 ac/ dc c haracteristics ................................ ................................ ................................ ................................ .... 35 confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 4 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. revision history rev. date author contents 0. 1 20 12/02/13 kevin hung first draft version. 0.2 2012/03/16 kevin hung f or pm 0.3 2012/0 9 / 07 kevin hung add pin number & ddr_phy(dll) power issue type issue solution f unction(interior of chip) mpll start - up time be solution & rom code flow power ddr_phy(dll) voltage of power supply t wo kinds of version confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 5 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. features ? high p erformance 32 - bit cpu ? mips32 24kec with ase dsp extension ? mmu embedded ? 16 kb instruction and 16 kb data cache ? embedded ice makes firmware debugging easier ? cpu o perating frequency up to 480mhz, on the fly programmable ? power m anagement features ? firmware configurable operating frequency of each functional block to meet best power budget ? internal power domain partition ? integrated c lock g enerator ? internal pll with spread spectrum capability ? 12mhz system/usb oscillator ? 32768 hz rtc oscillator ? scalable m emory b us a rchitecture ? 16 - bit ddr2 / ddr3 sdram bus, su pporting up to 2g b ddr sdram ? dram o perating frequency up to 400mhz without odt ? tunable ddr frequency on the fly for power saving ? sensor i nterface engine ? support up to 50 m pi xel s ccd / cmos image sensor ? support high speed serial interface like sub - lvds/m ipi/hispi up to 10 channels for most commercial cmos sensors including sony, panasonic, aptina, samsung, sharp and omnivision , etc. ? support parallel sensor interface for most com mercial ccd sensors including sony, panasonic, sharp and cmos sensors including aptina and omnivision ? support bt.601/656 video input ? support dual sensors input ( dual mipi version only ) ? support 12 - bit (serial) sensor data input ? support high speed serial int erface sensor pixel rate up to 576mp ixels/sec ? support continuous shot up to 10 fps for 16mp sensor ? support parallel interface sensor pixel clock up to 108mhz ? support movie ccd, and horizontal division ccd of sony ? support multiple field, line interleaved cc d of sharp confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 6 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. ? support smear reduction for ccd sensor ? built - in color pattern generation ? sensor black level clamping ? efficient defect concealment algorithm ? raw image sub - sample for video & high iso image ? flexible image analysis flow for ae, awb and af purpose ? p rogrammable histogram analysis ? automatic flicker detection ? r/g/b gamma lu t for sensor linearization correction ? in - pipeline l ens shading compensation technology ? in - pipeline color shading compensation technology ? in - pipeline geometric distortion co rrection te chnology ? in - pipeline color aberration co rrection technology ? support cmos sensor spatial crosstalk cancellation ? support in - frame dark frame subtraction with smart defect detection algorithm ? support rolling shutter correction for cmos sensor ? mechanical shutt er control ? flash light control ? image processing engine ? proprietary advanced anti - alias bayer cfa color interpolation ? flexible edge rendering, control and enhancement ? powerful noise reduction technology for still and video recording ? support motion compensat ed temporal filtering (mctf) for efficient video noise reduction ? support temporal noise reduction with ghost reduction ? r/g/b gamma lut ? high precision color correction matrix for srgb or specific color requirement ? brightness/contrast and hue/saturation adju stment ? specific color control technology ( p atent) ? 3d color conversion for specific color preference tuning ? false color suppression ? support wide dynamic range (wdr) for local illumination enhancement ? image manipulation engine ? high quality scaling engine for seamless digital zooming from 1/16x to 16x ? support thumbnail image generation confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 7 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. ? forward/inverse color space transform ? face detection engine ? very high speed face detection and tracking ? high accuracy under different light source ? programmable target data bas e ? digital image s tabilizer ? remove unintended hand movement from an image sequence ? single frame compensation for video (total compensation) ? a ccumulate frame compensation for video (smart compensation) ? m otion refresh rate 60hz ? interface search range up to ? 32 ? programmable total compensation range ? accommodate resolution 1080 p ? a djustable number of motion vectors for motion estimation . maximum 1024 motion vectors per process (16 regions x 64 blocks/region). ? lcd/tv display ? support dual display including lcd panel a nd hdmi/tv display simultaneous ly ? high performance scaling up/down engine, programmable gamma correction , color transform and color management for lcd or tv display ? separate osd for lcd panel and tv ? support digital lcd interface for auo , casio , cmi (all di gital panels will be supported) ? support 16 - bit rgb parallel interface (rgb565 or delta rgb) lcd panel up to 1024x1024 resolution ? support mipi dsi for mobile display ? support 90 rotation/flip/mirror ? support pal / ntsc video encoder (cvbs format) ? integrated 1 internal 10 - bit video dacs ? support digital interface bt.601/656/1120 output port ? 3.3v / 1.8v lcd / digital video out ? hdmi ? support hdmi v1. 3 a ? support ddc with maximum 100khz a ccess rate for cea - 861 - d format ? support cec ? support 16 bits pcm 32 khz, 44.1 khz, 48khz for maximum 2 channels audio output confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 8 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. ? graphic engine ? copy and paste ? geometric operation including mirror, flip and rotation ? arithmetic operation including addition, subtr action, color keying, logic operation and alpha blending ? support warping function ? support anti - alias affine transform ? support hardware acceleration for multi - frame processing ? cipher ? 64 - bit des, 3des, and aes - 128 ? both encryption and decryption ? big and littl e endian of input data ? h.264/avc c odec ? support e ncoder bp/mp, level 4.1 ? s upport encoder hp, level 4.2 ? support r eal - time capability for 1080p30, 720p60, 480p120 ? support full frame still capture while video recording ? h.264 high/main p rofile ? 1 reference pictu re for p - frame, 2 reference pictures for b - frame ? support video format mp4, avi, mov ? support bit rate control ? automatic frame sync for high frame rate ? motion estimation ? [ - 1 24 .75,+1 24 .75] search range in horizontal component ? [ - 28 .75, + 28 .75] search range in vertical component ? mb mode: 16x16, 16x8, 8x16, 8x8, skip, and direct (b - frame) ? f/w audio codec ? aac encode / decode (32khz, 48khz @ 192kbps) ? adpcm encode / decode ? noise cancellation for background noise, motor operation, and wind ? h/w audio codec ? stereo 16 - b its adc audio recording ? stereo 16 - bits dac audio playback ? programmable alc / noise gate l confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 9 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. ? audio sampling rate : 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48khz ? support dual microphone inputs ? on - chip speaker driver / stereo headphone drive ? jpeg codec ? supports motion jpeg 30fps @1080p30 video clip/playback function ? max. pixel clock 120mpixel / sec ? support iso/iec 10918 - 1 baseline jpeg compression/decompression. ? s till image maximum resolutions will be up to 65536x65536 pixels ? support input format: 422, 4 20, 411, 400, 211 ? jpeg supports d ownloadable quantization and huffman tables ? support exchangeable image file format (exif 2.2.3 and newer) ? support mpo file format for 3d image ? digital audio interface ? support i2s codec interface ? audio clock generator ? du al g raphic - based osd ? support 8 - bit palette and argb(4565 or 8565) osd architecture ? 256 colors simultaneously out of true color at 8 - bit palette osd ? 8 levels of opacity for 8 - bit palette osd ? programmable width & height to meet lcd/tv's resolution exactly ? pictur e in picture function ? dedicated 16 face frames for face detection function ? storage memory c ontroller ? s ecure digital card and sdio ? support sd 3.0 ? s upport uhs - i: uhs50, uhs104 (max. freq. 108mhz) ? support emmc and hot boot ? support eyefi for wireless connectio n ? multi - media card ? slc nand type flash ? usb ? fully compliant with usb2.0 device/host ? high speed (480mbps) supported ? optionally switchable to be fully compliant with usb 1.1 confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 10 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. ? support control / isochronous / interrupt and bulk transfer ? support pc camera mode ? ti mers ? rtc can be powered by separate backup battery and operating from 1. 5 v to 3 . 6 v ? watch dog timer ? 16 programmable hw timers support resolution up to 3mhz and 32 bits counter ? peripheral interface ? support i2c interface ? support 20 channels pwm including buil t - in 16 (4 sets) pattern generators for - stepping motor control. ? support gpio and flexible pwm interface with micro - stepping ? support programmable 3 - wired serial interface ? support spi for gyroscope reading ? support uart interface ? support 8 channels of 10 - bi t adc with touch panel interface (2 channels) , the max. sample rate up to 12.5 khz per channel ? on - chip b oot s trap l oader ? built - in on - chip mask rom ? user program can be stored in nand - type flash and external static memory is not necessary ? on - chip mask rom c an be disabled ? system can boot from spi flash , nand flash , memory card s, emmc and usb ? tri ple v oltage p ower s upply ? 1. 0 v core logic voltage ? 1.8v / 1.5v ddrii/ddriii sdram interface voltage ? 3.3v i/o interface and analog circuit voltage ? p ackage ? nt96650bg: 305 ball tfbga, 13x13 mm 2 confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 11 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. general description nt96650bg is a high image quality, high performance, power saving and cost effective digital still camera (dsc) and digital video camera (dv) controller with excellent digital still image capturing and video strea ming capabilities. it is t argeted for the application of vga to 50 m pixel dsc/dv resolutions. it can be easily adapted to many high speed cmos and conventional ccd image sensors with on chip programmable interface timing approach. the controller provides s ophisticated video processing methods with built - in hardware acceleration pipeline. this is essential for achieving high performance for per - shot, shot - to - shot, and continuous shooting pictures. the controller provides flexible mechanism for auto white bal ance, auto exposure and auto - focusing in order to better tradeoff hardware and software efforts over the performance. embedded h.264 video codec supports video recording up to full - hd 1080p30. the hdmi 1.3 tx is also equipped for hdtv output. rich storage interfaces are supported to make it ideal for the storage of still pictures and video streaming data. the usb2.0 high speed interface can upload/download the audio/video data efficiently to/from pc . confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 12 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. block diagram mic sensor interface sif / i 2 c gpio / adc audio codec / i 2 s interface dce dis boot rom memory card controller ipp / ipe face detection mips cpu ( 24 kec ) flash controller usb 2 . 0 uart hdmi tx tv encoder lcd / mipi controller ddrii / ddriii sdram cmos / ccd sensor timer / wdt pwm ( u - step ) key / battery detect sd card emmc / spi / nand flash rtc & power on / off rde graphic engine osd affine h . 264 video codec sdram controller zoom lens 32 . 768 k 12 m cipher engine ime ife / ise jpeg engine confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 13 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. pin configuration t fbga - 305 confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 14 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. pin no pin name pin no pin name pin no pin name pin no pin name a1 dr_d9 e19 i2c_sda k11 gnd r3 dr_a0 a2 dr_d14 f1 dr_d q m0 k12 gnd r17 jtag_trst # a3 fl_trig f2 dr_d q m1 k13 vddk r18 xtal_syso a4 sn_dgpio5 f3 vdd_dr k14 avdd_hdmi r19 xtal_sysi a5 sn_ s ck f6 sp _clk k16 avdd_dac t1 dr_a5 a6 sn_vd f7 pwm6 k17 tv_fsadj t2 dr_a3 a7 hsi_d0p f8 avdd_hsi_k k18 hdmi_tx0p t3 dr_a6 a8 hsi_d2p f9 avdd_hsi_rx k19 hdmi_tx0n t4 mc5 a9 hsi_d4p f10 vdd_hsi_io l1 dr_d2 t7 mc8 a10 hsi_ck0p f11 vdd_ vbat l2 dr_d3 t8 mc13 a11 hsi_d6p f12 vddk l3 dr_ras# t9 lcd9 a12 hsi_d8p f13 uart2_rx l4 vdd_dr t10 lcd5 a13 pwr_ en f1 4 vdd_io l6 pwm7 t11 lcd0 a14 xtal_rtc i f17 i2c_scl l7 pwm11 t12 ad_in3 a15 dgpio3 f18 a vd d_usb _fs l8 gnd t13 ad_in1 a16 dgpio0 f19 usb_ dp l9 gnd t16 avdd_spk a17 uart_tx g1 dr_d6 l10 gnd t17 avdd_aud a18 uart2_cts g2 dr_d1 l11 gnd t18 gnd_mpll a19 sb_dat23 g3 a vdd_dll l12 gnd t19 avdd_mpll b1 dr_d11 g4 vdd_dr l13 vddk u1 dr_a11 b2 dr_d12 g6 vdd_io l14 vddk u2 dr_a8 b3 pwm0 g7 pwm5 l16 sd_cap u3 dr_a4 b4 sn_dgpio6 g8 vdd_sn l17 vdd_sdli u4 mc2 b5 sn_dat g9 avdd_hsi_k l18 hdmi_txcp u5 mc9 b6 sn_hd g10 agnd_hsi l19 hdmi_txcn u6 mc4 b7 hsi_d0n g11 vdd_ rtc m1 dr_clk u7 mc15 b8 hsi_d2n g12 vddk m2 dr_clk# u8 lcd12 b9 hsi_d4n g13 pwm16 m3 dr_cas# u9 lcd8 b10 hsi_ck0n g14 pwm19 m4 dr_reset # u10 lcd4 b11 hsi_d6n g16 avdd_usb_li m6 lcd20 u11 lcd1 b12 hsi_d8n g17 agnd_usb m7 lcd19 u12 ad_in0 b13 pwr_sw 2# g18 usb_ rref m8 gnd u13 avdd_adc b14 xt al_rtc o g19 usb_d m m9 gnd u14 ad_in y b15 reset# h1 dr_d0 m10 lc d16 u15 agnd_adc b16 uart_rx h2 dr_d7 m11 lcd14 u16 agnd_spk b17 pwm15 h3 avdd_dr_1v m12 agnd_dsi u17 aud_vmidx b18 remote_rx h4 vdd_dr m13 mc26 u18 mic_rinn b19 sb_ck23 h6 vddk m14 mc27 u19 mic_rinp c1 dr_dqs1 h7 vddk m16 mc19 v1 dr_a7 c2 dr_dqs1# h 8 agnd_hsi m17 mc18 v2 dr_a13 c3 pwm1 h9 gnd m18 mc17 v3 vdd_mc c4 sn_dgpio7 h10 gnd m19 mc16 v4 mc1 c5 sn_dgpio4 h11 gnd n1 dr_ba1 v5 mc10 c6 sn_cs h12 pwr_sw3 n2 dr_cke v6 mc7 c7 sn_pxclk h13 uart2_rts n3 dr_we# v7 mc12 c8 hsi_d1p h14 pwm17 n4 dr_c s# v8 lcd11 c9 hsi_d3p h16 hdmi_rext n6 lcd18 v9 lcd7 c10 hsi_d5p h17 agnd_hdmi n7 lcd21 v10 lcd3 c11 hsi_d7p h18 hdmi_tx2p n8 vddk v11 dsi_d0p c12 hsi_d9p h19 hdmi_tx2n n9 vddk v12 dsi_ckp c13 dgpio2 j1 dr_dqs0# n10 lcd15 v13 dsi_d1p c14 pwr_ sw1 j2 dr_dqs0 n11 lcd13 v14 ad_in x c15 pwm14 j3 vdd_dr n12 vdd_dsi_io v15 tp_xm c16 dgpio1 j4 dr_vref n13 mc24 v16 hp_l c17 pwm12 j6 pwm8 n14 jtag_tms v17 agnd_aud c18 sb _ cs3 j7 vddk n16 mc22 v18 mic_linn c19 sb _ cs2 j8 gnd n17 mc23 v19 mic_linp d1 dr_d8 j9 gnd n18 mc21 w1 dr_a12 d2 dr_d15 j10 gnd n19 mc20 w2 dr_a9 confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 15 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. d3 pwm3 j11 gnd p1 dr_ba0 w3 mc0 d4 pwm2 j12 testen p2 dr_ba2 w4 mc3 d7 sn_mclk j13 pwm18 p3 dr_a2 w5 mc6 d8 hsi_d1n j14 uart2_tx p6 lcd22 w6 mc11 d9 hsi_d3n j16 agnd_dac p7 lcd17 w7 mc14 d 10 hsi_d5n j17 tv_cvbs p8 vddk w8 lcd10 d11 hsi_d7n j18 hdmi_tx1p p9 vdd_lcd w9 lcd6 d12 hsi_d9n j19 hdmi_tx1n p10 vdd_lcd w10 lcd2 d13 pwr_sw 4 k1 dr_d4 p11 dsi_cap w11 dsi_d0n d16 pwm13 k2 dr_d5 p12 avdd_dsi_k w12 dsi_ckn d17 vbus i k3 a gnd_dll p13 mc 25 w13 dsi_d1n d18 ddc_sda k4 vdd_dr p14 vdd_io w14 ad_in2 d19 ddc_scl k6 pwm9 p17 jtag_tck w15 tp_yp e1 dr_d13 k7 pwm10 p18 jtag_tdi w16 hp_r e2 dr_d10 k8 gnd p19 jtag_tdo w17 spk_p e3 pwm4 k9 gnd r1 dr_a1 w18 spk_n e17 hdmi_plug k10 gnd r2 dr_a10 w 19 mic_bias e18 hdmi_cec confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 16 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. pin descriptions i = input port with schmitt trigger o = output port with normal driving/sinking i/o = bi - directional port with normal driving/sinking and schmitt input mvi/o = multi voltage bi - direction port with schmitt input hsi = high speed serial interface with multi voltage input port i/o sw = bi - directional port with strong driving/sinking and wide schmitt input range i/o w = bi - directional port with wide schmitt input range i/o s = bi - directional port with strong driv ing/sinking i/o ss = bi - directional port with strong driving/sinking i/o z = bi - directional port with large pull/down resistor i/o 5vt = bi - directional port with normal driving/sinking and schmitt input od = open drain output with normal sinking i/od = bi - dir ectional port, open drain output lvd = low voltage detect function pin p/u = internal pull - up p/d = internal pull - down ai = analog input port ai 5vt = analog 5v tolerant input port ao = analog output port ai /o = analog bi - directional port h = output high l = output low p = power or ground note : * means this pin h as interrupt ed function . confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 17 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. nt96 650b g 305 pins total : 144 pins alternative gpio: 44 total pins system interface ( 9 ) pin no. name type reset descriptions r19 xtal_sysi ai - crystal input for s ystem osc illator . ( 12mhz ) r18 xtal_syso a o - output for system oscillator . b15 reset# lvd p/u system reset . connect a capacitor to ground for reset time control. j12 testen i i p/d test m ode enable. keep lo w f or norm al oper at ion. r17 jtag_ trst # / p_ gpi o [ 31 ] * io i p/u jtag test logic reset(active low). n14 jtag_ tms / p_ gpi o [ 32 ] * io i p/d jtag test mode select. p17 jtag_ tck / p_ gpi o [ 33 ] * io i p/d jtag test clock input. p18 jtag_ tdi / p_ gpi o [ 34 ] * io i p/d jtag test data input. p19 jtag_ tdo / p_ gpi o [ 35 ] * io i p/d jtag test data output. rtc & power button controller ( 7 ) pin no. name type default descriptions a14 xtal_rtci ai - crystal input for real time clock oscillator. ( 32 . 768 k hz ) . b14 xtal_rtco a o - output for real time clock oscillator. c14 pwr_sw1 * a i i p/d power on/off signal input. (on/off switch use) b13 pwr_sw2 * # a i i p/u power on/off signal input . (falling edge trigger) h12 pwr_sw3 i 5vt z i p/d power on/off signal input. ( 5v tolerance input for vbusi use) d13 pwr_sw4 a i i p/d power on/off sign al input. (bettery in use) a13 pwr_en a o - p ower enable signal output. * pwr_sw can trigger interrupt (share rtc interrupt). if this pin isn?t used, novatek recommends connecting this pin to gnd. dram interface ( 4 8 ) pin no. name type reset descriptions m4 dr_reset # o - reset signal output for ddr3 dram. m1 dr_clk o - m2 dr_clk # o - dram differential c lock output . n2 dr_cke o - dram c lock e nable . n4 dr_c s# m3 dr_cas# o - dram control signals confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 18 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. l3 dr_ras# n3 dr_we# j4 dr_vref ai - d ram ref erence voltage input. p1 dr_ba0 n1 dr_ba1 p2 dr_ba 2 o - dram b ank select . r3 dr_a0 r1 dr_a1 p3 dr_a2 t2 dr_a3 u3 dr_a4 t1 dr_a5 t3 dr_a6 v1 dr_a7 u2 dr_a8 w2 dr_a9 r2 dr_a10 u1 dr_a11 w1 dr_a1 2 v2 dr_a1 3 o - dram address bus. f1 dr_dqm0 f2 dr_dqm1 o - dram d ata m ask : dqm 0 corresponds to dq0 - dq7 and dqm 1 corresponds to dq8 - dq15. j2 dr_dqs0 j1 dr_dqs 0# c1 dr_dqs1 c2 dr_dqs1 # i/o - dram data strobe. dqs0 corresponds to dq0 - dq7 and dq s 1 corresponds to dq8 - dq15. h1 dr_d0 g2 dr_d1 l1 dr_d2 l2 dr_d3 k1 dr_d4 k2 dr_d5 g1 dr_d6 h2 dr_d7 i/o - dram d ata bus input/output , lower byte. ( each bits of lower byte may be permute d to make routing simpler). d1 dr_d8 a1 dr_d9 e2 dr_d10 b1 dr_d11 b2 dr_d12 e1 dr_d13 a2 dr_d14 d2 dr_d15 i/ o - dram d ata bus input/output, upper byte. (each bits of upper byte may be permute d to make routing simpler) sensor interface ( 33 ) pin no. name type reset d escriptions b7 hsi _d0 n / hsi i p/d high s peed differential sensor interface and parallel confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 19 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. s_ gpi [0] a7 hsi _d 0p / s_ gpi [1] d8 hsi _d 1n / s_ gpi [2] c8 hsi _d 1p / s_ gpi [3] b8 hsi _d 2n / s_ gpi [4] a8 hsi _d 2p / s_ gpi [5] d9 hsi _d 3n / s_ gpi [6] c9 hsi _d 3p / s_ gpi [7] b9 hsi _d 4n / s_ gpi [8] a9 hsi _d 4p / s_ gpi [9] b10 hsi_ck0n / s_ gpi [10] a10 hsi_ck0p / s_ gpi [11] d10 hsi _d 5n / s_ gpi [12] c10 hsi _d 5p / s_ gpi [13] b11 hsi _d 6n / s_ gpi [14] a11 hsi _d 6p / s_ gpi [15] d11 hsi _d 7n / s_ gpi [16] c11 h si _d 7p / s_ gpi [17] b12 hsi _d 8n / s_ gpi [18] a12 hsi _d 8p / s_ gpi [19] d12 hsi _d 9n / s_ gpi [20] c12 hsi _d 9p / s_ gpi [21] interface. ( when sensor interface is configured as high speed differential sensor interface, the clock lane should be a dedicated d ifferential lane . and ea ch data lanes may be permute d in established group, refer to below table) d7 sn_mclk / s_ gpio [24] mv i/o s i p/d programmable clock output for sensor c7 sn_pxclk / s_ gpio [25] mv i/o s i p/d sensor p ixel clock input a6 sn_vd / mv i/o i p/d s ensor vertical sync input / output confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 20 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. s_ gpio [26] b6 sn_hd / s_ gpio [27] mv i/o i p/d s ensor horizontal sync input / output c6 sn _cs / spi3_cs / p_ gpio [56] mvios i p/u general serial interface 0 or serial peri pheral interface 3 chip select a 5 sn_ sc k / spi3_clk / i2c_scl / p_ gpio [57] mvio d i p/u general serial interface 0 or serial peripheral interface 3 clock output. i2c - bus clock output(open drain io structure) b5 sn_dat / spi3_do / i2c_sda / p_ gpio [58] mvio d i p/u general serial interface 0 or serial peripheral interface 3 data output. i2c - bus data input / output(open drain io structure) c5 sn_dgpio4* mvio i p/ d general purpose input / output a4 sn_dgpio5* mvio i p/ d general purpose input / output b4 spi3_di / sn_shutter / sn_dgpio6* mvio i p/ d serial peripheral interface 3 data input. shutter signal input from sensor c4 sn_flash / sn_dgpio7* mvio i p/ d flash signal input from sensor note*: the pin can trigger interrupt. note 1 : the inpu t voltage of hsi corresponds to g vdd_sn. note2 : the mvi/o voltage of sensor interface corresponds to vdd_sn. name lvds hispi mipi csi parallel (12 bits) ccir601 (16 bits) ccir601 (8 bits) s_gpi[0] hsi_d0n slvs_d0n i csi_d0n i sn_d0 i s_gpi[1] hsi_ d0 p slvs_d0p i csi_d0p i sn_d1 i s_gpi[2] hsi_d 1 n slvs_d1n i csi_d1n i sn_d2 i s_gpi[3] hsi_d 1p slvs_d1p i csi_d1p i sn_d3 i s_gpi[4] hsi_d 2 n slvs_d2n i csi_d2n i sn_d4 i ccir_y0 i s_gpi[5] hsi_d 2p slvs_d2p i csi_d2p i sn_d5 i ccir_y 1 i s_gpi[6] hsi_d 3 n slvs_d3n i csi_d3n i sn_d6 i ccir_y2 i s_gpi[7] hsi_d 3p slvs_d3p i csi_d3p i sn_d7 i ccir_y3 i s_gpi[8] hsi_d 4 n sn_d8 i ccir_y4 i s_gpi[9] hsi_d 4p sn_d9 i ccir_y5 i s_gpi[10] hsi_ ck 0n slvs_ckn i csi_ckn i sn _d10 i ccir_y6 i s_gpi[11] hsi_ ck0p slvs_ckp i csi_ckp i sn_d11 i ccir_y7 i s_gpi[12] hsi_d 5 n ccir_c0 i ccir_yc0 i s_gpi[13] hsi_d 5p ccir_c1 i ccir_yc1 i s_gpi[14] hsi_d 6 n ccir_c2 i ccir_yc2 i s_gpi[15] hsi_d 6p ccir_c3 i ccir_yc3 i s_gpi[16] hsi_d 7 n ccir_c4 i ccir_yc4 i s_gpi[17] hsi_d 7p ccir_c5 i ccir_yc5 i s_gpi[18] hsi_d 8 n ccir_c6 i ccir_yc6 i s_gpi[19] hsi_d 8p ccir_c7 i ccir_yc7 i s_gpi[20] hsi_d 9 n ccir_vd i ccir_vd i s_gpi[2 1] hsi_d 9p ccir_hd i ccir_hd i s_gpi[24] sn_mclk sn_mclk o sn_mclk o sn_mclk o s_gpi[ 25 ] sn_pxclk sn_pxclk i sn_pxclk i s_gpi[ 26 ] sn_vd sn_vd i/o sn_vd i/o s_gpi[ 27 ] sn_hd sn_hd i/o sn_hd i/o sn_dgpio4 ccir_clk i ccir_clk i confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 21 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. memory card interface ( 2 9 ) pin no. name type reset descriptions l16 sd_cap p - internal supply voltage decoupling for sdio interface. (3.3/1.8v switchable, default 3.3v) w3 mc0 / c_gpio[0] mv i/o i p/u v4 mc1 / c_gpio[1] mv i/o i p/u u4 mc2 / c_gpio[2] mv i/o i p/ u w4 mc3 / c_gpio[3] mvi/o i p/u u6 mc4 / c_gpio[4] mvi/o i p/u t4 mc5 / c_gpio[5] mv i/o i p/u w5 mc6 / c_gpio[6] mvi/o i p/u v6 mc7 / c_gpio[7] mvi/o i p/u t7 mc8 / c_gpio[8] mv i /o i p/u u5 mc9 / c_gpio[9] mvi/o i p/u v5 mc10 / c_gpio[10] mvi/o i p/u w6 mc11 / c_gpio[11] mv i/o i p/u v7 mc12 / c_gpio[12] mvi/o i p/ d t8 mc13 / c_gpio[13] mvi/o i p/d w7 mc14 / c_gpio[14] mv i/o i p/u u7 mc15 / c_gpio[15]* mv i/o i p/u m 19 mc16 / c_gpio[16] i/o s i p/d m18 mc17 / c_gpio[17] i/o i p/u m17 mc18 / c_gpio[18] i/o i p/u m16 mc19 / c_gpio[19] i/o i p/u n19 mc20 / c_gpio[20] i/o i p/u memory card interface (see below table ) confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 22 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. n18 mc21 / c_gpio[21]* i/o i p/u n16 mc22 / c_gpio[22]* i/os i p/ d n17 mc23 / c_gp io[23]* i/o i p/u n13 mc24 / c_gpio[24]* i/o i p/u p13 mc25 / c_gpio[25]* i/o i p/u m13 mc26 / c_gpio[26]* i/o i p/u m14 mc27 / c_gpio[27]* i/o i p/u note*: the pin can trigger interrupt. note1 : the mvi/o voltage of mc0~15 corresponds to vdd_mc . note2 : the io voltage of mc 16~21 corresponds to sd_cap , it could be switched between 3.3/1.8v by the register . memory card interface pinmux table name nand flash sd/mmc/ emmc sd spi flash i2s mc0 nand _d0 i/o emmc_d0 i/o spi_do/d0 i/o mc1 nand _d1 i /o emmc_d1 i/o spi_di/d1 i/o mc2 nand _d2 i/o emmc_d2 i/o spi_clk o mc3 nand _d3 i/o emmc_d3 i/o spi_wp/d2 i/o mc4 nand _d4 i/o emmc_d4 i/o spi_hold/d3 i/o mc5 nand _d5 i/o emmc_d5 i/o mc6 nand _d6 i/o emmc_d6 i/o m c7 nand _d7 i/o emmc_d7 i/o mc8 nand_cs 0# o spi_cs # o mc9 nand_cs 1# o emmc_clk o mc10 nand _we # o mc11 nand _re # o emmc_cmd i/o mc12 nand _cle o mc13 nand _ale o mc14 nand _ wp# o mc1 5 nand _ rdy i mc16 sd_clk o mc17 sd_cmd i/o mc18 sd_d0 i/o mc19 sd_d1 i/o mc20 sd_d2 i/o mc21 sd_d3 i/o mc22 sdio_clk o spi_clk o i2s_mclk o mc23 sdio_cmd i/o spi_cs# o i2s_bclk i/o mc24 sdio_d0 i/o spi_di i i2s_sync o mc25 sdio_d1 i/o spi_do o i2s_do o mc26 sdio_d2 i/o i2s_di i mc27 sdio_d3 i/o lcd interfa ce ( 23 ) p in no. name type reset descriptions confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 23 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. t11 lcd0 / l _ gpio[0] / bs0 mv i/ o i p/d u11 lcd1 / l _ gpio[1] / bs1 mvi/o i p/d w10 lcd2 / l _ gpio[2] / bs2 mvi/o i p/d lcd signal bus / bs2..0 : boot_src the boot source setting description: 0x0: nand with rs ecc 0x1: boot card (select by boot_card) 0x2: emmc (sdio2_2) 0x3: usb full speed 0x4: spi flash 0x5: usb high speed 0x6: nand with hamming ecc 0x7: bmc (spi) v10 lcd3 / l _ gpio[3] / bs3 mvi/o i p/d lcd signal bus / bs3 : reserved for f/w (mpll control flow) bs6..3 is for ic debugging setting. please keep low at reset signal ris ing edge. u10 lcd4 / l _ gpio[4] / bs4 mvi/o i p/d lcd signal bus / bs4 : boot_card boot card select 0: sdio 1: sdio2 (sdio2_2) t10 lcd5 / l _ gpio[5] / bs5 mvi/o i p/d lcd signal bus / bs5 : ejtag_sel ejtag select 0: gpio (trst, tms, tck, tdi, tdo are gpi o) 1: ejtag w9 lcd6 / l _ gpio[6] / bs6 mvi/o i p/d lcd signal bus / bs6 : mpll_clk_sel select clock source of pll. 0: a pll clock output (from a pll clock) 1: bypass a pll (from external clock) v9 lcd7 / l _ gpio[7] / bs 7 mvi/o i p/d lcd signal bus / bs7 : e mmc_buswidth emmc boot bus width 0: 4 bits data bus 1: 8 bits data bus u9 lcd8 / l _ gpio[8] mv i/o i p/d t9 lcd9 / l _ gpio[9] mvi/o i p/d w8 lcd10 / l _ gpio[10] mvi/o i p/d v8 lcd11 / l _ gpio[11] mvi/o i p/d lcd signal bus u8 lcd12 / l _ gpio[12] / bs 8 mv i/o i p/d lcd signal bus / bs8 : emmc_bootmode emmc boot mode 0: single rate + backward timing 1: dual rate + high speed timing n11 lcd13 / l _ gpio[13] / bs 9 mvi/o i p/d lcd signal bus / bs9 : emmc_ddr_data_order emmc ddr data order 0: odd byte (1 st byte) f irst 1: even byte (2 nd byte) first m11 lcd14 / mvi/o i p/d lcd signal bus/ bs 10 : mips_debug_mode_sel confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 24 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. l_gpio[14] / bs 10 enable nt96650 enters cpu debug mode. internal cpu state will be outputted to debug port on storage interface (mc[18..0]) 0: normal mo de 1: cpu debug mode bs10 for ic debugging setting. please keep low at reset signal rising edge. m11 lcd14 / l _ gpio[14] mvi/o i p/d n10 lcd15/ l _ gpio[15] mvi/o i p/d m10 lcd16 / l _ gpio[16] mvi/o i p/d p7 lcd17 / l _ gpio[17] mvi/o i p/d n6 lcd18 / l _ gpio[18] * mvi/o i p/d m7 lcd19 / l _ gpio[19] * mvi/o i p/d m6 lcd20 / l _ gpio[20] mvi/o i p/d n7 lcd21 / l _ gpio[21] mvi/o i p/d p6 lcd22 / l _ gpio[22] mvi/o i p/d lcd signal bus note1 : the mvi/o voltage of lcd interface corresponds to vdd_lcd . l cd interface pinmux table name ccir(8 bits) serial rgb ccir(16 bits) i80/m68 ccir & rgb (secondary panel) mpu s erial (secondary panel) lcd0 ccir_yc0 o rgb_d0 o ccir_y0 o mpu_d0 i/o lcd1 ccir_yc1 o rgb_d1 o ccir_y1 o mpu_d1 i/o lcd2 ccir_yc2 o rgb_d 2 o ccir_y2 o mpu_d2 i/o lcd3 ccir_yc3 o rgb_d3 o ccir_y3 o mpu_d3 i/o lcd4 ccir_yc4 o rgb_d4 o ccir_y4 o mpu_d4 i/o lcd5 ccir_yc5 o rgb_d5 o ccir_y5 o mpu_d5 i/o lcd6 ccir_yc6 o rgb_d6 o ccir_y6 o mpu_d6 i/o lcd7 ccir_yc7 o rgb_d7 o ccir_y7 o mpu_d7 i/o lcd8 ccir_clk o rgb_clk o ccir_clk o mpu_te i lcd9 ccir_vd o rgb_vd o ccir_vd o mpu_cs# o lcd10 ccir_hd o rgb_hd o ccir_hd o mpu_rs o lcd11 ccir_de o mpu_wr# o lcd12 ccir_c0 o mpu_rd# o rgb_yc0 o lcd13 ccir_c1 o mpu_d8 i/o rgb_yc1 o mpu_sdo o lcd14 ccir_c2 o mpu_d9 i/o rgb_yc2 o mpu_sdi i lcd15 ccir_c3 o mpu_d10 i/o rgb _yc3 o mpu_cs o lcd16 ccir_c4 o mpu_d11 i/o rgb _yc4 o mpu_rs o lcd17 ccir_c5 o mpu_d12 i/o rgb _yc5 o mpu _clk o lcd18 ccir_c6 o mpu_d13 i/o rgb _yc6 o mpu_sdio i/o lcd19 ccir_c7 o mpu_d14 i/o rgb _yc7 o mi_te i lcd20 lcd_cs o mpu_d15 i/o rgb _clk o lcd21 lcd_clk o mpu_d16 i/o rgb _vd o lcd22 lcd_dat o mpu_d17 i/o rgb _hd o confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 25 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. pwm ( 20 ) pin no. name type reset descriptions b3 pwm 0 / m e_ shut0 / p_gpio[36] i/o i p/d c3 pwm 1 / me_shut1 / p_gpio[37] i/o i p/d d4 pwm 2 / p_gpi o[38] i/o i p/d d3 pwm 3 / p_gpio[39] i/o i p/d pwm output pin. mechanical shutter control output. micro - stepping control module 1. e3 pwm 4 / p_gpio[40] i/o i p/d g7 pwm 5 / p_gpio[41] i/o i p/d f7 pwm 6 / p_gpio[42] i/o i p/d l 6 pwm 7 / p_gpio[43] i/o i p/d pwm output pin. micro - stepping control module 2. serial peripheral interface j6 pwm 8 / p_gpio[44] i/o i p/d k6 pwm 9 / p_gpio[45] i/o i p/d k7 pwm 10 / p_gpio[46] i/o i p/d l7 pwm 11 / p_gpio[47] i/o i p/d pwm output pin. micro - stepping control module 3. c17 pwm 12 / p_gpio[48] i/o i p/d d16 pwm 13 / p_gpio[49] i/o i p/d c15 pwm 14 / p_gpio[50] i/o i p/d b17 pwm 15 / p_gpio[51] i/o i p/d pwm output pin. micro - stepping control module 4. g13 pwm 16 / m e_ shut0 / p_gpio[52] i/o i p/d h14 pwm 17 / m e_ shut 1 / p_gpio[53] i/o i p/d pwm ou tput pin. mechanical shutter control output. j13 pwm 18 / p_gpio[54 ] * i/o i p/d pwm output pin. g14 pwm 19 / p_gpio[55 ] * i/o i p/d pwm output pin. confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 26 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. name pwm m - shutter u - stepping spi pwm 0 pwm0 o me_shut0 o ustp1_a o pwm1 pwm1 o me_shut1 o ustp1_b o pwm2 pwm2 o ustp1_c o pwm3 pwm3 o ustp1_d o pwm4 pwm4 o ustp2_a o spi3_clk o pwm5 pwm5 o ustp2_b o spi3_cs# o pwm6 pwm6 o ustp2_c o spi3_do o pwm7 pwm7 o ustp2_d o spi3_di o pwm8 pwm8 o ustp3_a o pwm9 pwm9 o ustp3_b o pwm10 pwm10 o ustp3_c o pwm11 pwm11 o ustp3_d o pwm12 pwm12 o ustp4_a o pwm13 pwm13 o ustp4_b o pwm14 pwm14 o ustp4 _c o pwm15 pwm15 o ustp4_d o pwm16 pwm16 o me_shut0 o pwm17 pwm17 o me_shut1 o pwm18 pwm18 o pwm19 pwm19 o peripheral i/o ( 19 ) pin no. name type reset descriptions e19 i2c _ sda / p_gpio[0] * i/o d i p/u i2c - bus clock output(open drain io structure) f17 i2c _ scl / p_gpio[1] * i/o d i p/u i2c - bus data input / output(open drain io structure) c19 sb _ cs2 / spi3_cs / p_gpio[7]* i/o i p/ u serial interface chip select 2 serial peripheral interfa ce 3 chip select output c18 sb _ cs3 / spi3_di / p_gpio[8 ] * i/o i p/ u serial interface chip select 3 serial peripheral interface 3 data input b19 sb _ ck23 / spi3_clk / p_gpio[9 ] * i /o i p/d serial interface clock 2 & 3 serial peripheral interface 3 clock output a19 sb _ dat23 / spi3_do / p _gpio[10 ] * i/o i p/d serial interface data 2 & 3 serial peripheral interface 3 data output a17 uart_ t x / p _ gpio [15] i/o o uar t transmit b16 uart_rx / p _ gpio [16]* i/o i p/u uart receive j14 uart 2 _ t x / spi2_c s / p _ gpio [17]* i/o i p/u uar t 2 transmit serial peripheral interface 2 chip select output f13 uart 2 _rx / spi2_clk / p _ gpio [1 8 ]* i/o i p/u uart 2 receive serial peripheral interface 2 clock output confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 27 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. h13 u a rt 2 _rts / spi2_do / p_gpio[ 19]* i/o i p/ u uart 2 request to send serial peripheral interface 2 data output a18 uart 2 _cts / spi 2 _di / p_gpio[20]* i/o i p/u uart 2 clear to send serial peripheral interface 2 data input b18 remote_rx / picnt3 / p_gpio[ 2 5]* i/o ss i p/u infrared remote - c ontrol received data pulse counter 3 input a3 fl_ trig / s_gpio[28] i/o i p/d flash light trigger control f6 sp_clk / picnt4 / s_gpio[ 29 ] * i/o s s i p/d clock output for micro - stepping motor control pulse counter 4 input a16 picnt 1 / dgpio0 * i/o s w i p/d pulse counter 1 input c16 picnt 2 / dgpio1 * i/o s w i p/d pulse counter 2 input c13 sd_cd# / dgpio2 * i/o s w i p/ u card detect input pin a15 sd_wp# / dgpio3 * i/o s w i p/ u write protect input pin adc interface ( 8 ) pin no. name t ype reset descriptions u12 ad_in 0 ai - general adc 0 input with buffer. t13 ad_in 1 * ai - general adc 1 input with configurable trigger function w14 ad_in 2 * ai - general adc 2 input with configurable trigger function t12 ad_in 3 ai - general adc 3 input with buffer. v14 ad_in x ai - general adc x input and touch panel cont r ol i nt erf ace u14 ad_in y ai - general adc y input and touch panel cont r ol i nt erf ace w15 t p_yp ai - touch panel contr ol i nt erf ace v15 tp_xm ai - touch panel contr ol i nt erf ace audio c odec ( 10 ) p in no. name type reset descriptions w19 mic_bias ao - microphone working bias output. u19 mic_rinp ai - right channel microphone differential input posit i ve side. u18 mic_rinn ai - right channel microphone differential input negative side. v1 9 mic_linp ai - left channel microphone differential input posit i ve side. v18 mic_linn ai - left channel microphone differential input negative side. u17 vmidx ao - decoupling for audio codec reference voltage. connect 4.7uf capacitor to ground. w16 hp _ r ao - right channel headphone output. (or line out) v16 hp _ l ao - left channel headphone output. (or line out) w17 spk _p ao - speaker output of right channel confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 28 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. w18 spk_n ao - speaker output of left channel tv interface ( 2 ) p in no. name type reset des criptions j17 tv_cvbs ao - video data output composite video output . k17 tv_fsadj ai - full screen adjust pin tv dac full - scale adjust control pin. a 470 ? /1% resistor connected between this pin and gnd controls the full - scale output current on the tv_cv bs output. mipi dsi ( 7 ) p in no. name type reset descriptions p11 dsi_cap p - internal supply voltage decoupling for dsi lp mode circuit. v12 dsi_ckp ao - w12 dsi_ckn ao - mipi dsi differential clock lane output v11 dsi_d0p ao - w11 dsi_d0n ao - v13 dsi_d1p ao - w13 dsi_d1n ao - mipi dsi differentia l data lane input / output hdmi (1 3 ) p in no. name type reset descriptions l18 hdmi_ txcp l19 hdmi_ txcn ao - tmds low voltage differential signal ou t put clock k18 hdmi_ tx0p k19 hdmi_ tx0n j18 hdmi_ tx1p j19 hdmi_ tx1n h18 hdmi_ tx2p h19 hdmi_ tx2n ao - tmds low voltag e differential signal ou t put data h16 hdmi_rext ai - voltage swing adjust. connect 1.2 k ? /1% resistor to hdmi gnd e18 hdmi_ cec / p _gpio[ 27 ]* i/o 5vt i p/u consumer e lectronics control . cec is 5v tolerance input. d18 ddc_sda / p _ gpio[ 28 ] i/o d 5vt i p/u display data channel sda. d dcsda is 5v tolerance input. d19 ddc_scl / p _ gpio[ 29 ] i/o d 5vt i p/u display data channel scl. ddcscl is 5v tolerance input. e17 hdmi _ plug / p _ gpio[ 30 ] * i/o 5vt i p/d hot plug detect. hotplug is 5v tolerance input. confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 29 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. usb device interface (4) pin no. name type reset descriptions d17 vbus i * i 5vt z i p/ d usb v bus input . this pin is 5v tolerance input f19 usb_dp ai/o - usb fs/hs differential dat a plus (d+) g19 usb_dm ai/o - usb fs/hs differential data minus (d - ) g18 usb_rref ai - usb reference resistor. connect 1 2k ? /1% resistor to gnd power ( 7 3 ) pin no. name type descriptions f 12, g12, h6, h7, j7, k13, l13, l14, n8, n9, p8 v dd k (11) p core p ower f14, g6, p14 v dd_io (3) p i/o pad power h9, h10, h11, j8, j9, j10, j11, k8, k9, k10, k11, k12, l8, l9, l10, l11, l12, m8, m9 gnd (19) p digital ground f3, h4, l4, g4, k4, j3 vdd_d r (6) p dram i/o power. (1.8v for ddrii; 1.5v for ddr iii .) h3 avdd_dr_ 1v p analog 1.0v power for ddr phy g3 a vdd_dll (1) p dll power . (3.3v power for hv version, 1.5/1.8v for lv version) k3 a gnd_dll (1) p g orund for dll g11 vdd_rtc (1) p rtc power f11 vdd_vbat (1) p battery input for power button controller v3 vdd_ mc (1) p m ulti - level io power for memory card f 8, g9 avdd_ hsi_k p analog 1.0v power for hs i core power f9 avdd_hsi_rx p analog 3. 3 v power for hsi receiver f10 vdd_hsi_io p m ulti - level input power of h si g10, h8 agnd_hsi (2) p ground for high speed interface g8 v dd_sn p m ulti - level io power for sensor interface p 9, p10 vdd_lcd (2) p m ulti - level io power for lcd interface l17 vdd_sdli p ldo ? s input power for card io p12 a vdd_dsi_k p analog power for mipi dsi core n12 vdd_dsi _io p ldo ? s input power for mipi dsi l p io m12 a gnd _dsi p ground for mipi dsi u13 avdd_adc p analog 3.3v p ower for adc u15 agnd_adc p ground for adc k16 avdd_dac p analog 3.3v power for tv dac j16 agnd _dac p ground for tv dac t17 avdd_aud p analog 3.3v power for audio c odec v17 agnd_aud p ground for audio codec t16 avdd_spk p analog 3.3v power for speaker amplifier confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 30 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. u16 agnd_spk p ground for speaker amplifier k14 avdd_hdmi p analog hdmi interface power h17 agnd_hdmi p ground for hdmi interface g 16 avdd_usb _li p ldo ? s input power for usb phy f 18 vdd_usb _ fs p usb full speed transceiver power g 17 agnd_usb p ground for usb t19 avdd_mpll p m ultiple pll analog power t18 agnd_mpll p pll analog power confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 31 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. package outline tfbga - 305 confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 32 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. electrical characteristics absolute maximum ratings item s ymbol rating unit supply voltage of 1 .0 v core power v dd k - 0.3 ~ +1. 2 v supply voltage of dram i/o v dd_ dr - 0.3 ~ +2.1 v supply voltage of 3.3v digital i/o v dd_io , v dd_rtc , v dd_ vbat , v dd_ sdli , v dd_ d si_io - 0.3 ~ +3.8 v supply voltage of multi - level i/o v d d_ mc , v dd_ hsi_io , v dd_ sn , v dd_ lcd - 0.3 ~ +3.8 v supply voltage of 1.0v analog block av dd_ dr_1v , av dd_ hsi_k , av dd_ dsi_k , av dd_ mpll - 0.3 ~ +1.2 v supply voltage of 1.5/1.8v analog block * av dd_ d ll , av dd_hdm i , av dd_ usb_li - 0.3 ~ +2.1 v supply voltage of 3. 3v analog block * av dd_ d ll , a v dd_ hsi_rx , av dd_usb _ fs , av dd_adc , av dd_dac , av dd_aud , a v dd_ spk , - 0.3 ~ +3.8 v input/output voltage i/o - 0.3 ~ v dd_io +0.3 v input voltage (5v tolerant) i/o 5vt - 0.3 ~ +5.8 v operating ambient temperature t opr - 10 ~ 70 0 c stor age temperature t stg - 55 ~ 125 0 c * av dd_ d ll : supply 3.3v for hv version, 1.5/1.8v for lv version comment stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional o peration of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliabili ty. esd performance model standard classification note human body mode(hbm) mil - std - 883g method 3015.7 class : 2 2k~3kv machine mode(mm) jedec specification eia/ jesd22 - a11 5 class : b 200~400v cdm mode(cdm) jedec specification jesd22 - c101 confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 33 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. latch - up i mmunity model standard classification note latch up jedec specifi cation jesd - 78 a class : i 200ma recommended operating conditions symbol parameter min. typ. max. unit conditions v dd k core logic operating voltage 0.9 1. 0 1. 1 v v dd _dr ddrii dram inter face operating voltage 1.7 1.8 1.9 v ddrii dram v dd _dr ddriii dram interface operating voltage 1.425 1.5 1.575 v ddr iii dram v dd _io general i/o interface operating voltage 3.0 3.3 3.6 v v dd _ rtc rtc operating voltage 1.5 - 3.6 v v dd _ rt c rtc maintenanc e voltage 1 - 3.6 v v dd _vbat power controller operating voltage 1.5 - 3.6 v v dd_ sdli i/o of sd card operating voltage 3.0 3.3 3.6 v v dd_ dsi_io ldo of mipi dsi operating voltage 3.0 3.3 3.6 v v dd_mc i/o of memory card interface operating voltage 1.6 2 3.3 3.6 v 1.8v~3.3v v dd_ hsi_io input of high speed interface operating voltage 1.62 3.3 3.6 v 1.8v~3.3v v dd _sn i/o of sensor interface operating voltage 1.62 3.3 3.6 v 1.8v~3.3v v dd_lcd i /o of lcd interface operating voltage 1.62 3.3 3.6 v 1.8v~3.3v av dd_ dr_1v core logic of ddr phy operating voltage 0.9 1. 0 1. 1 v av dd_ hsi_k core logic of high speed interface operating voltage 0.9 1. 0 1. 1 v av dd_ dsi_k core logic of mipi dsi operating voltage 0.9 1. 0 1. 1 v a v dd _mpll mpll operating v oltage 0.9 1. 0 1. 1 v av dd_ d ll dll operating voltage 3.0 3.3 3.6 v hv version av dd_ d ll dll operating voltage 1.425 1.5 1.9 v lv version a v dd _hdmi transceiver of hdmi 1.425 1.5 1.9 v confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 34 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. operating voltage a v dd _usb_li ldo of usb phy operating voltage 1.425 1.5 1.9 v a v dd_ hsi_rx receiver of high speed interface operating voltage 3.0 3.3 3.6 v a v dd _usb_fs transceiver of usb full speed operating voltage 3.0 3.3 3.6 v a v dd _adc adc operating voltage 3.0 3.3 3.6 v a v dd _dac video dac operating voltage 3.0 3.3 3.6 v a v dd _aud audio codec operating voltage 3.0 3.3 3.6 v a v dd _spk speaker amplifier operating voltage 3.0 3.3 3.6 v confidential free datasheet http://www.0pdf.com
nt96 650 bg - es 2012 - 09 - 17 - 35 - with respect to the information represented in this document, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non - infringement, or assume s any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. ac/ dc characteristics tbd confidential free datasheet http://www.0pdf.com

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